1. Field of the Invention
This invention generally relates to analog-to-digital converters (ADCs) and, more particularly, to a system and method for calibrating the mean frequency of a voltage controlled oscillator (VCO) based ADC.
2. Description of the Related Art
ADC converters are widely used in electronics circuits. The performance of an ADC is dependent on the performance of its components. For a monolithic ADC, the components are transistors, such as metal-oxide-semiconductor field effect transistors (MOSFETs) and bipolar junction transistors (BJTs). Year after year, the unity gain frequency (fT) of transistors has been improved by advances in device engineering. Although, an improvement in fT translates into an improvement in inverter delay, it does not necessary improve all the performance metrics critical for an analog circuit design. For instance, the output resistance of devices has degraded over the years. ADC design involves both analog and digital circuit blocks. The analog blocks involved in conventional ADC architectures like pipelined, flash, etc. may not take full advantage of improvements in fT. However, one recent ADC architecture—the VCO based ADC—benefits from a direct relationship between ADC performance and the fT of its devices. Hence, this ADC architecture will greatly benefit from this trend.
FIG. 1 is a schematic block diagram of a VCO based ADC (prior art). Such an ADC can achieve very high performance, comparable to other wide-spread conventional ADC architectures. A differential input signal drives a pseudo-differential VCO directly or through a voltage-to-current (V-to-I) block 100. The multiphase outputs of each VCO, 102 and 104, are sampled by a clock and converted to an equivalent digital word, by phase-to-digital blocks 106 and 108. A difference of the two digital outputs is taken to obtain the ADC output. During normal operation, as the input voltage to either of the two VCO increases, the corresponding oscillation frequency of that VCO also increases.
FIG. 2 is a graph depicting an exemplary relationship between VCO control voltage and output frequency (prior art). The phase-to-digital blocks compute the sum of level changes (both high to low and low to high) within each clock cycle of the sampling clock, for each of the n phases of an n-phase VCO.
FIG. 3 is a schematic diagram depicting an exemplary phase-to-digital circuit (prior art).
FIG. 4 is a graph depicting the relationship between the sampling clock frequency (Fs) and VCO frequency (prior art). The digital output of each phase-to-digital block is proportional to VCO frequency, which is the input frequency for the phase-to-digital block. However, the values wrap around between 0 and the full scale output. The full scale output is set by the number of phases in the VCO. Clearly, input signals causing the VCO to remain within each the band of operation (0 to FS/2, FS/2 to Fs, FS to 3FS/2, etc.) are digitized linearly, except for weak non-linearities due to V2I, the VCOs, and phase-to-digital blocks. Whenever the VCO frequency spills over from one band of operation to an adjacent band, another source of non-linearity is triggered due to the wrapping of phase-to-digital output, which becomes a dominant source as the spillover increases. Hence, the VCOs should be constrained within only one band during normal operation. The dynamic range is maximized when the digital output of the phase-to-digital blocks is centered at half of its full scale output, referred to herein as the mid-reference frequency. For example, in the band between FS/2 and FS, the VCO frequency is centered around 3*FS/4. This mean VCO frequency is set by the VCO oscillation frequency when V2I is driven by an input common-mode voltage, or in other words, when the differential input is absent. Due to process variations, the mean frequency can be significantly higher or lower than the desired 3*FS/4. A VCO mean frequency calibration loop is therefore required to adjust the VCO parameters so that the mean VCO frequency is equal to the mid-reference frequency.
FIG. 5 is a schematic block diagram depicting a VCO based ADC that addresses the problem of VCO mean frequency calibration. In this design, a third replica VCO is used, which is driven by common-mode input voltage. The frequency measurement of this replica VCO is used to drive the VCO mean frequency towards mid-reference. However, this approach increases the power consumption due to the addition of a VCO and a phase-to-digital converter to the ADC. The design also suffers from errors due to a mismatch between the nominal and the replica VCO. The reference designators associated with this figure are described in FIG. 3 of U.S. Pat. No. 8,542,138, the entirety of which is incorporated herein by reference.
It would be advantageous if the mean frequency of a VCO based ADC could be calibrated without the use of an additional replica VCO.